Classes, Inheritance, Polymorphism
VLSI → SystemVerilog for Verification
OOP on top of Verilog
SystemVerilog adds real object-oriented programming on top of Verilog's hardware description constructs: you write a class transaction, a class driver extends base_driver, and override virtual methods. UVM (the industry-standard verification methodology) is built entirely on top of these three ideas — no OOP means no UVM, which means no DV job. This is mandatory intake material at companies like Cadence, Synopsys, Intel, and NVIDIA India.
The one keyword that makes polymorphism work
class base_driver;
virtual task drive(); $display("base drive"); endtask
endclass
class axi_driver extends base_driver;
task drive(); $display("AXI drive"); endtask // overrides base_driver::drive
endclass
base_driver h;
h = new axi_driver();
h.drive(); // prints "AXI drive" — NOT "base drive"Even though
h is declared as a base_driver handle, calling h.drive() runs axi_driver's override — because drive() is virtual. Drop the virtual keyword and this same code would call base_driver::drive() instead, silently. Virtual methods and $cast (for safely converting a base handle back to a derived type) are common interview ground precisely because this distinction is easy to get wrong.Try it — which method actually runs?
base_driver h;
h = new axi_driver();
h.drive(); // prints "AXI drive"
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