Immediate vs Concurrent Assertions
VLSI → Assertion-Based Verification (SVA)
Design rules the simulator checks automatically
SystemVerilog Assertions let you state design rules that the simulator checks for you, instead of eyeballing waveforms. Immediate assertions fire inside procedural code exactly like an if-check — evaluated once, right now, at the line they appear on. Concurrent assertions are clocked — they sample signals on a clock edge and can check behavior across many cycles, not just a single instant.
// Immediate — checked once, right here, in procedural code
always @(posedge clk) begin
assert (addr < 1024) else $error("address out of range");
end
// Concurrent — checked every clock edge, across time
assert property (@(posedge clk) req |-> ##[1:3] ack);Why this distinction is the first SVA question asked
"Have you written SVA?" is a standard DV screening question, and immediate-vs-concurrent is the very first follow-up — because picking the wrong kind for the job is a real, common mistake: an immediate assertion can't express "ack must follow within 3 cycles" (that's inherently a multi-cycle, clocked check), and a concurrent assertion is overkill for a simple procedural sanity check on a single variable.
Try it — when does each one actually evaluate?
Evaluated at every sampled clock edge, and can check a pattern that spans multiple future edges before it reports pass or fail.
Completion saves automatically after you read through to the end.
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