Latches & Flip-Flops
VLSI → Sequential Logic
Combinational vs sequential
Every circuit you've built so far was combinational — outputs depend only on current inputs. A sequential circuit adds memory: the output depends on current inputs AND what happened before. That memory is a latch or a flip-flop.
SR latch
| S, R | Result |
|---|---|
| 1, 0 | Q goes to 1 and stays there after S returns to 0 |
| 0, 1 | Q goes to 0 and stays there |
| 0, 0 | Q holds its previous state — the memory state |
| 1, 1 | forbidden — Q and Q' both go to 0, contradicting Q' = NOT Q |
| S | R | Q | Q' |
|---|---|---|---|
| 0 | 0 | hold | hold |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | forbidden | forbidden |
Why this works · explanation & key points
The simplest memory element. Two cross-coupled NOR (or NAND) gates with two inputs: S (Set) and R (Reset).
The latch is level-sensitive: as long as S or R is high, the output keeps responding — there's no clock controlling when the change happens.
D latch (transparent latch)
| En | D | Q |
|---|---|---|
| 0 | 0 | hold |
| 0 | 1 | hold |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Why this works · explanation & key points
Adds an Enable input to the SR latch. When Enable=1, Q follows D (transparent — look through the latch and you see D). When Enable=0, Q freezes at whatever D was when Enable fell (opaque).
D flip-flop (edge-triggered)
Why this works · explanation & key points
A D flip-flop samples D on a specific clock edge (rising or falling) and holds that value for a full clock cycle. Unlike a latch, it only changes at the edge — never in between.
Nearly all synchronous RTL is built from D flip-flops on a single clock. Latches are avoided because their level-sensitive behavior makes timing analysis harder and causes transparent-latch races.
Click "Clock ↑" to send a rising edge. Q captures D at that moment and holds it until the next edge.
JK flip-flop
| J | K | Q(next) |
|---|---|---|
| 0 | 0 | hold |
| 0 | 1 | 0 (reset) |
| 1 | 0 | 1 (set) |
| 1 | 1 | toggle |
Why this works · explanation & key points
Solves the SR latch's forbidden state. J=Set, K=Reset, and J=K=1 toggles Q instead of being forbidden.
T flip-flop
| T | Q(next) |
|---|---|
| 0 | hold |
| 1 | toggle |
Why this works · explanation & key points
The simplest toggle: one input T. T=0 → Q holds. T=1 → Q toggles every clock edge. Used in counters because it naturally divides the clock frequency by 2.
With T=1 constantly, each clock edge flips Q — that's a divide-by-2 counter.
The interview question
Why not latches? A transparent latch opens a path from input to output for half a clock cycle — synthesis tools struggle to constrain that, and it can cause combinational loops if not carefully controlled.
Practice
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