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01VLSI Landscape & Design Flow0/4

What is VLSI & why it mattersFree preview Analog vs Digital vs Mixed-signal Frontend vs Backend VLSI The chip design flow (spec → sign-off)

02Combinational Logic0/7

Boolean AlgebraFree preview Number Systems & Binary Arithmetic Digital Codes Logic Gates K-map Minimization Arithmetic Circuits Mux, Decoders & Encoders

03Sequential Logic0/6

Latches & Flip-FlopsFree preview Finite State Machines Counters Registers & Shift Registers Clock dividers & synchronizers (CDC intro)Reset: synchronous vs asynchronous

04CMOS & Transistor-Level Basics0/7

MOSFET as a switchFree preview CMOS inverter & its VTC CMOS logic gates (pull-up / pull-down)Short-channel effects (why small transistors misbehave)Why simulators don't use the square-law equation Static vs dynamic power Low-power design: clock & power gating

05Verilog & RTL Basics0/5

Verilog syntax: modules, ports, types, operatorsFree preview always blocks: blocking vs non-blocking, parameters RTL → hardware mapping & synthesizability Testbenches: $display, $monitor, waveforms EDA Playground / Verilator workflow

06Memory Types & On-Chip Memory0/4

SRAM vs DRAMFree preview ROM, EPROM, EEPROM & Flash (NAND vs NOR)Memory in RTL ($readmemh, BRAM inference)FIFOs & dual-port RAM

07Static Timing Analysis (STA) Basics0/4

Setup & hold time, clock-to-QFree preview Combinational delay & slack Critical path & maximum frequency Clock skew & false paths

08Communication Protocol RTL0/6

UART frame format (8N1)Free preview Baud rate generators, oversampling Self-checking testbenches Loopback verification I2C protocol (start/stop, addressing, ACK)SPI protocol (CPOL/CPHA, MOSI/MISO/SCLK/CS)

09Datapath + Parameterized RTL0/4

ALU operations, flags, overflowFree preview Parameterized modules, generate blocks Directed + random testbench Coverage thinking (manual)

10FPGA Bring-up (Tang Nano 9K)0/5

Gowin EDA + open Yosys/nextpnr flowFree preview Pin constraint files (CST/PCF)PWM + motor driver (L298N)PS/2 keyboard + 7-segment Logic synthesis: RTL → gate netlist

11Display + Frame-Buffer RTL0/4

VGA timing (sync, porches)Free preview Block RAM inference Sprite rendering Bitmap framebuffer

12Computer Architecture & RISC-V CPU0/5

RISC vs CISC & the pipelining ideaFree preview RISC-V RV32I ISA 5-stage pipeline (IF/ID/EX/MEM/WB)Hazard detection + forwarding Running real programs (assembler → hex)

13Bus Protocols + IP Integration0/4

AXI4-Lite / APB / AHBFree preview Bus master + slave testbench Memory map + address decoding Protocol assertions

14Verifying Real Designs (Verilator)0/4

Verilator C++ test harnessFree preview Cycle-accurate co-simulation Virtual PTY / socat for serial Regression scripting

15SystemVerilog for Verification0/4

Classes, inheritance, polymorphismFree preview Constrained randomization Mailboxes, semaphores, events Assertions (SVA) + functional coverage

16Coverage-Driven Verification0/4

Directed vs random & the coverage-driven loopFree preview Code coverage (statement/branch/expression/toggle/FSM)Functional coverage (covergroups, coverpoints, bins, cross)Coverage closure: combining code + functional

17Assertion-Based Verification (SVA)0/4

Immediate vs concurrent assertionsFree preview Sequences & properties Implication & temporal operators Assertion coverage (cover property)

18Verification Planning & Management0/4

The verification plan (vplan)Free preview Testbench architecture Regression & test-suite management Coverage sign-off & closure tracking

19UVM + SoC Integration0/6

UVM components: agent, driver, monitor, scoreboardFree preview UVM phases + factory + config_db SoC = CPU + AXI peripherals + bootloader End-to-end RTL → simulation → bring-up EDA flow scripting (TCL / Makefile / Python) — role-specific UVM RAL (register abstraction layer)

01VLSI Landscape & Design Flow0/4

What is VLSI & why it mattersFree preview Analog vs Digital vs Mixed-signal Frontend vs Backend VLSI The chip design flow (spec → sign-off)

02Combinational Logic0/7

Boolean AlgebraFree preview Number Systems & Binary Arithmetic Digital Codes Logic Gates K-map Minimization Arithmetic Circuits Mux, Decoders & Encoders

03Sequential Logic0/6

Latches & Flip-FlopsFree preview Finite State Machines Counters Registers & Shift Registers Clock dividers & synchronizers (CDC intro)Reset: synchronous vs asynchronous

04CMOS & Transistor-Level Basics0/7

MOSFET as a switchFree preview CMOS inverter & its VTC CMOS logic gates (pull-up / pull-down)Short-channel effects (why small transistors misbehave)Why simulators don't use the square-law equation Static vs dynamic power Low-power design: clock & power gating

05Verilog & RTL Basics0/5

Verilog syntax: modules, ports, types, operatorsFree preview always blocks: blocking vs non-blocking, parameters RTL → hardware mapping & synthesizability Testbenches: $display, $monitor, waveforms EDA Playground / Verilator workflow

06Memory Types & On-Chip Memory0/4

SRAM vs DRAMFree preview ROM, EPROM, EEPROM & Flash (NAND vs NOR)Memory in RTL ($readmemh, BRAM inference)FIFOs & dual-port RAM

07Static Timing Analysis (STA) Basics0/4

Setup & hold time, clock-to-QFree preview Combinational delay & slack Critical path & maximum frequency Clock skew & false paths

08Communication Protocol RTL0/6

UART frame format (8N1)Free preview Baud rate generators, oversampling Self-checking testbenches Loopback verification I2C protocol (start/stop, addressing, ACK)SPI protocol (CPOL/CPHA, MOSI/MISO/SCLK/CS)

09Datapath + Parameterized RTL0/4

ALU operations, flags, overflowFree preview Parameterized modules, generate blocks Directed + random testbench Coverage thinking (manual)

10FPGA Bring-up (Tang Nano 9K)0/5

Gowin EDA + open Yosys/nextpnr flowFree preview Pin constraint files (CST/PCF)PWM + motor driver (L298N)PS/2 keyboard + 7-segment Logic synthesis: RTL → gate netlist

11Display + Frame-Buffer RTL0/4

VGA timing (sync, porches)Free preview Block RAM inference Sprite rendering Bitmap framebuffer

12Computer Architecture & RISC-V CPU0/5

RISC vs CISC & the pipelining ideaFree preview RISC-V RV32I ISA 5-stage pipeline (IF/ID/EX/MEM/WB)Hazard detection + forwarding Running real programs (assembler → hex)

13Bus Protocols + IP Integration0/4

AXI4-Lite / APB / AHBFree preview Bus master + slave testbench Memory map + address decoding Protocol assertions

14Verifying Real Designs (Verilator)0/4

Verilator C++ test harnessFree preview Cycle-accurate co-simulation Virtual PTY / socat for serial Regression scripting

15SystemVerilog for Verification0/4

Classes, inheritance, polymorphismFree preview Constrained randomization Mailboxes, semaphores, events Assertions (SVA) + functional coverage

16Coverage-Driven Verification0/4

Directed vs random & the coverage-driven loopFree preview Code coverage (statement/branch/expression/toggle/FSM)Functional coverage (covergroups, coverpoints, bins, cross)Coverage closure: combining code + functional

17Assertion-Based Verification (SVA)0/4

Immediate vs concurrent assertionsFree preview Sequences & properties Implication & temporal operators Assertion coverage (cover property)

18Verification Planning & Management0/4

The verification plan (vplan)Free preview Testbench architecture Regression & test-suite management Coverage sign-off & closure tracking

19UVM + SoC Integration0/6

UVM components: agent, driver, monitor, scoreboardFree preview UVM phases + factory + config_db SoC = CPU + AXI peripherals + bootloader End-to-end RTL → simulation → bring-up EDA flow scripting (TCL / Makefile / Python) — role-specific UVM RAL (register abstraction layer)

Logic Synthesis: RTL → Gate Netlist

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