MOSFET as a Switch

VLSI → CMOS & Transistor-Level Basics

Videos 30–34 · nMOS & pMOS — the two transistor types

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The switch model

Type	ON condition	OFF condition
NMOS	gate HIGH (≥ Vth)	gate LOW
PMOS	gate LOW (≤ VDD − \|Vtp\|)	gate HIGH

NMOS and PMOS are complementary — when one is ON the other is OFF for the same gate voltage. This is the key property that makes CMOS logic work.

Why this works · explanation & key points

A MOSFET is a voltage-controlled switch — the gate voltage controls whether current can flow between drain and source. You don't need the full physics to design logic, the switch model is enough.

Try it — NMOS

NMOS switch

         VDD
          │
Gate ──┤├── Drain → OFF — blocking
          │
         GND

OFF — blocking

NMOS: gate ≥ Vth → channel forms → current flows source to drain.

Try it — PMOS

PMOS switch

         VDD
          │
Gate ──┤◁── Drain → ON — conducting
          │
         GND

ON — conducting

PMOS: gate ≤ VDD − |Vtp| → channel forms → current flows source to drain.

Why complementary matters

NMOS + PMOS together — complementary pair

PMOS (pull-up)

NMOS (pull-down)

OFF

Output

Exactly one transistor is ON at any time — no direct path from VDD to GND in steady state → zero static power.

Why this works · explanation & key points

Put PMOS on top (connected to VDD) and NMOS on bottom (connected to GND), drive both gates with the same signal — at any steady input, exactly one transistor is ON. There's never a direct path from VDD to GND, so no static current flows and no static power is wasted.

Threshold voltage (V_th)

Interview tip: "What happens to leakage as V_thdecreases?" → leakage grows exponentially (I_leak ∝ e^(–V_th/nV_T)). That's why low-power chips use high-V_tcells in non-critical paths.

Why this works · explanation & key points

V_th is the minimum gate voltage that turns an NMOS on (or the maximum that keeps a PMOS on). Lowering V_th makes transistors switch faster but increases leakage current when they should be off. This tradeoff is what drives multi-V_t design strategies at advanced nodes.

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MOSFET as a Switch

VLSI → CMOS & Transistor-Level Basics

Videos 30–34 · nMOS & pMOS — the two transistor types

Loading…

The switch model

Type	ON condition	OFF condition
NMOS	gate HIGH (≥ Vth)	gate LOW
PMOS	gate LOW (≤ VDD − \|Vtp\|)	gate HIGH

NMOS and PMOS are complementary — when one is ON the other is OFF for the same gate voltage. This is the key property that makes CMOS logic work.

Why this works · explanation & key points

A MOSFET is a voltage-controlled switch — the gate voltage controls whether current can flow between drain and source. You don't need the full physics to design logic, the switch model is enough.

Try it — NMOS

NMOS switch

         VDD
          │
Gate ──┤├── Drain → OFF — blocking
          │
         GND

OFF — blocking

NMOS: gate ≥ Vth → channel forms → current flows source to drain.

Try it — PMOS

PMOS switch

         VDD
          │
Gate ──┤◁── Drain → ON — conducting
          │
         GND

ON — conducting

PMOS: gate ≤ VDD − |Vtp| → channel forms → current flows source to drain.

Why complementary matters

NMOS + PMOS together — complementary pair

PMOS (pull-up)

NMOS (pull-down)

OFF

Output

Exactly one transistor is ON at any time — no direct path from VDD to GND in steady state → zero static power.

Why this works · explanation & key points

Threshold voltage (V_th)

Interview tip: "What happens to leakage as V_thdecreases?" → leakage grows exponentially (I_leak ∝ e^(–V_th/nV_T)). That's why low-power chips use high-V_tcells in non-critical paths.

Why this works · explanation & key points

Completion saves automatically after you read through to the end.

Next lesson →