RISC vs CISC & the Pipelining Idea
VLSI → Computer Architecture & RISC-V CPU
Simple and uniform vs dense and varied
RISC (Reduced Instruction Set Computer) keeps every instruction simple and the same fixed length — typically just load/store plus a handful of ALU ops — so they pipeline cleanly. CISC (Complex Instruction Set Computer) packs more work into each instruction, at the cost of variable length and harder-to-pipeline decode logic. This distinction, and "what is pipelining," are standard computer-architecture warm-up questions before any CPU-design interview.
Why uniform length is what actually enables pipelining
// RISC-style: 3 simple, fixed-length instructions lw x1, 0(x10) // load a[0] add x1, x1, x2 // add b sw x1, 0(x10) // store result // Hypothetical CISC-style: 1 instruction doing the same work ADDMEM [x10], x2 // load-add-store fused into one op
The CISC instruction is denser, but a decoder can't cleanly overlap "fetch the next instruction" with "decode this one" when instructions vary wildly in length and complexity — you don't know where the next instruction even starts until you've fully decoded the current one. RISC's fixed length and simple structure removes that ambiguity, which is exactly what lets fetch/decode/execute for different instructions overlap in a pipeline — the core idea behind every modern CPU, and the reason RISC-V in particular is teachable at the RTL level.
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