Setup & Hold Time, Clock-to-Q
VLSI → Static Timing Analysis (STA) Basics
The three flip-flop timing numbers
| Parameter | Meaning |
|---|---|
| Setup time (T_setup) | data must be stable this long BEFORE the clock edge |
| Hold time (T_hold) | data must stay stable this long AFTER the clock edge |
| Clock-to-Q (T_clk-Q) | output Q appears this long AFTER the clock edge |
Why this works · explanation & key points
Every flip-flop has three timing parameters that define how it behaves around a clock edge:
Violate setup and the flip-flop misses the data — it may capture a wrong value or go metastable. Violate hold and it captures the new value too, overwriting what was just latched.
Visualizing the windows
Move the slider left — data arriving too close to the clock edge causes a setup violation.
Why this works · explanation & key points
Drag the slider to move your data arrival time and see which window you fall into:
Computing setup slack
Required time = T_clk − T_setup
Slack = Required − Arrival (positive = pass, negative = violation)
Why this works · explanation & key points
The path: Launch FF → (T_clk-Q delay) → combinational logic → (T_comb delay) → Capture FF input. The capture FF needs the data at least T_setup before the next clock edge.
Metastability — what actually happens on a violation
Why this works · explanation & key points
When data changes inside the setup-hold window, the flip-flop's internal nodes are both trying to go high and low at once — it enters a metastable state where the output is neither 0 nor 1. It eventually resolves, but the resolution time is unpredictable; if it overflows the clock period, the next stage sees garbage.
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