SRAM vs DRAM
VLSI → Memory Types & On-Chip Memory
What are they?
DRAM — 1 transistor + 1 capacitor per cell, capacitor leaks → must be refreshed every few milliseconds. Dense and cheap.
Why this works · explanation & key points
Every memory chip stores bits, but the circuit holding one bit is completely different between SRAM and DRAM — and that difference decides where each type lives in a computer.
SRAM — the 6T cell
Why this works · explanation & key points
Two cross-coupled inverters latch the value (4 transistors); two access transistors connect the cell to the bitlines when the wordline is asserted. The inverters keep fighting each other to hold Q=1 or Q=0 — no charge leaks away, so no refresh is needed.
Flip between 0 and 1 — the circuit holds it statically.
DRAM — the 1T1C cell
Why this works · explanation & key points
One access transistor routes charge onto a tiny capacitor. Capacitors leak — without periodically reading and rewriting every row (a refresh cycle), the charge bleeds away and the data is gone.
Tick = time passing. Refresh restores the charge before the capacitor discharges fully.
Side-by-side comparison
| Property | SRAM | DRAM |
|---|---|---|
| Cell size | 6 transistors | 1T + 1 capacitor |
| Density | Low (bigger per bit) | High (very dense) |
| Speed | Fast (~1–5 ns) | Slower (~60–100 ns) |
| Refresh | None needed | Required every 64 ms |
| Power (idle) | Higher leakage | Lower (but refresh overhead) |
| Cost per bit | Expensive | Cheap |
| Where used | L1/L2/L3 cache, register files | Main memory (RAM) |
The memory hierarchy
Why this works · explanation & key points
Every computer layers these memories by speed vs. cost:
Closer to the CPU core = smaller and faster (SRAM). Further away = denser and cheaper (DRAM → Flash).
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