UART Frame Format (8N1)
VLSI → Communication Protocol RTL
Videos 23–24 · FSM Modeling (UART RX is an FSM)
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What UART is
UART is the "Hello World" peripheral — usually the first thing brought up on a new chip. Drawing the 8N1 frame and explaining oversampling is a near-certain fresher whiteboard question.
Why this works · explanation & key points
UART sends data one bit at a time over a single wire. "Asynchronous" means no shared clock — both sides must agree on a baud rate beforehand. 8N1 is the most common configuration: 8 data bits, No parity, 1 stop bit.
The 8N1 frame — click to explore
Data byte (hex):0x41 = 'A'
Click any bit to see what it represents. Change the byte to watch the data bits update.
Why this works · explanation & key points
A UART frame is exactly 10 bits: 1 start + 8 data (LSB first) + 1 stop.
Bit-by-bit breakdown
| Field | Role |
|---|---|
| Start bit (0) | idle line is HIGH — a falling edge (HIGH→LOW) tells the receiver a frame is starting and syncs its sampling counter |
| Data bits D0–D7 | sent LSB first — e.g. 0x41 ('A' = 0100 0001) is D0=1, D1=0, D2=0, D3=0, D4=0, D5=0, D6=1, D7=0 |
| Stop bit (1) | line returns to HIGH for at least 1 bit period, giving the receiver time to reset before the next start bit |
How the receiver finds bit centres
CLKS_PER_BIT = system_clock_Hz / baud_rate
Sample at count = CLKS_PER_BIT / 2 // midpoint
Interview maths: "50 MHz clock, 9600 baud — what is CLKS_PER_BIT?" → 50,000,000 / 9600 ≈ 5208, rounded. The fractional error accumulates over 10 bits but must stay within ½ bit period — at 2% tolerance, 9600 baud is very comfortable.
Why this works · explanation & key points
Without a shared clock the receiver can't know exactly when each bit starts, so it oversamples: run an internal counter at 16× the baud rate, reset it on the start bit's falling edge, and sample at count 8 — the midpoint of each bit, where the signal is most stable.
Completion saves automatically after you read through to the end.
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