UVM Components: Agent, Driver, Monitor, Scoreboard
VLSI → UVM + SoC Integration
The verification lingua franca
A UVM testbench moves data through a fixed pipeline: Sequence → Sequencer → Driver (drives DUT pins) → DUT → Monitor (samples DUT pins back into transactions) → Scoreboard (compares actual vs. expected). Driver + Monitor + Sequencer, bundled together, form an Agent — you typically have one agent per protocol your DUT speaks. This dominates fresher DV interviews at companies like Intel, NVIDIA, Qualcomm, AMD, and Samsung India.
Try it — what does each component actually do?
Generates the abstract transaction — e.g. "write 0xDEAD to address 0x100" — with no knowledge of DUT pins at all.
Completion saves automatically after you read through to the end.
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